Functional description
The AS7C1024B is a high performance CMOS 1,048,576-bit Static
Random Access Memory (SRAM) device organized as 131,072 words x 8
bits. It is designed for memory applications where fast data
access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20
ns with output enable access times (tOE) of 5/6/7/8 ns are ideal
for high performance applications. Active high and low chip enables
(CE1, CE2) permit easy memory expansion with multiple-bank systems.
Features
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS
• 6T 0.18u CMOS technology
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
