GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 67,108,864-bits. It is internally configured as a
quad-bank DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK). Each of
the 16,777,216-bit banks is organized as 2,048 rows by 256 columns
by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed number
of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ
or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed
(BA0, BA1 select the bank, A0-A10 select the row). The address bits
registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on positive edge of
system clock
• Internal pipelined operation; column address can be changed every
clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto
Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
