PSoC Functional Overview
The PSoC family consists of many On-Chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
system components with one low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, and programmable interconnects. This architecture
enables the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data memory,
and configurable I/O are included in a range of convenient pinouts
and packages.
Features
■ Powerful Harvard Architecture Processor:
❐ M8C Processor Speeds up to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC® Blocks)
❐ Six Analog Type “E” PSoC Blocks Provide:
• Single or Dual 8-Bit ADC
• Comparators (up to four)
❐ Up to Eight Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• One Shot, Multi Shot Mode Support in Timers and PWMs
• PWM with Deadband Support in One Digital Block
• Shift Register, CRC, and PRS Modules
• Full Duplex UART
• Multiple SPI Masters or Slaves, Variable Data Length Support: 8
to 16-Bit
• Can be Connected to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
❐ Shift Function Support for FSK Detection
❐ Powerful Synchronize Feature Support. Analog Module Operations
can be Synchronized by Digital Blocks or External Signals.
■ High Speed 10-Bit SAR ADC with Sample and Hold Optimized for
Embedded Control
■ Precision, Programmable Clocking:
❐ Internal ± 5% 24/48 MHz Oscillator across the Industrial
Temperature Range
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal/External Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory:
❐ Up to 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles
❐ Up to 1K Byte SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Optimized CapSense® Resource:
❐ Two IDAC Support up to 640 µA Source Current to Replace External
Resistor
❐ Two Dedicated Clock Resources for CapSense:
• CSD_CLK: 1/2/4/8/16/32/128/256 Derive from SYSCLK
• CNT_CLK: 1/2/4/8 Derive from CSD_CLK
❐ Dedicated 16-Bit Timers/Counters for CapSense Scanning
❐ Support Dual CSD Channels Simultaneous Scanning
■ Programmable Pin Configurations:
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on
all GPIO
❐ Up to 38 Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources:
❐ I2C™ Slave, Master, and MultiMaster to 400 kHz
❐ Supports Hardware Addressing Feature
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
❐ Supports RTC Block into Digital Peripheral Logic
