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EP4SGX360NF45C4N 920 I/O FPGA Field Programmable Gate Array

    Buy cheap EP4SGX360NF45C4N 920 I/O FPGA Field Programmable Gate Array from wholesalers
     
    Buy cheap EP4SGX360NF45C4N 920 I/O FPGA Field Programmable Gate Array from wholesalers
    • Buy cheap EP4SGX360NF45C4N 920 I/O FPGA Field Programmable Gate Array from wholesalers

    EP4SGX360NF45C4N 920 I/O FPGA Field Programmable Gate Array

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    Brand Name : Intel / Altera
    Model Number : EP4SGX360NF45C4N
    Certification : Lead free / RoHS Compliant
    Price : USD 9000-10000 pcs
    Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card
    Supply Ability : 118 pcs
    Delivery Time : 3-5 Day
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    EP4SGX360NF45C4N 920 I/O FPGA Field Programmable Gate Array

    EP4SGX360NF45C4N Field Programmable Gate Array Stratix IV GX


    Product AttributeAttribute Value
    Intel
    FPGA - Field Programmable Gate Array
    Stratix IV GX
    353600
    14144
    920 I/O
    900 mV
    0 C
    + 70 C
    SMD/SMT
    FBGA-1932
    Tray
    Data Rate:600 Mb/s to 8.5 Gb/s
    Series:Stratix IV GX
    Brand:Intel / Altera
    Maximum Operating Frequency:600 MHz
    Moisture Sensitive:Yes
    Number of Transceivers:48 Transceiver
    Product Type:FPGA - Field Programmable Gate Array
    Factory Pack Quantity:12
    Subcategory:Programmable Logic ICs
    Total Memory:22564 kbit
    Tradename:Stratix
    Part # Aliases:974495

    Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without
    compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other
    high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.
    ■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium
    ■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel
    ■ 72,600 to 813,050 equivalent LEs per device
    ■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers
    ■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz
    ■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device
    ■ Programmable power technology that minimizes power while maximizing device performance

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