EP2SGX90EF1152C3N FPGA - Field Programmable Gate Array
RC0201FR-0710KL VQFN-HR-15 Programmable Logic ICs
Features This section lists the Stratix II GX device features.
■ Main device features:
● TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers with
performance up to 550 MHz
● Up to 16 global clock networks with up to 32 regional clock
networks per device region
● High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
● Up to four enhanced PLLs per device provide spread spectrum,
programmable bandwidth, clock switch-over, real-time PLL
reconfiguration, and advanced multiplication and phase shifting
● Support for numerous single-ended and differential I/O standards
● High-speed source-synchronous differential I/O support on up to
71 channels
● Support for source-synchronous bus standards, including SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and
CSIX-L1
● Support for high-speed external memory, including quad data rate
(QDR and QDRII) SRAM, double data rate (DDR and DDR2) SDRAM, and
single data rate (SDR) SDRAM
