Universal Software Defined Radio Platform,USRP-LW 2950, 120MHz
The USRP-LW 2950 is a high-performance, scalable software-defined
radio (SDR) platform for designing and deploying next-generation
wireless communication systems. It consists of one USRP-LW X310,
two WBX-LW 120MHz RF daughter boards and one OCXO,
The USRP-LW 2950 hardware architecture combines two expanded bandwidth daughter
board slots with a bandwidth of up to 40M from 50 MHz to 2.2 GHz.
And it features multiple high-speed interfaces to choose from
(PCIe, Gigabit/10 Gigabit Ethernet ports), as well as a
resource-rich, user-programmable Kintex-7 FPGA. In addition, the USRP-LW 2950 uses an open source cross-platform UHD driver, with a large number
of development frameworks, compatible reference architectures, and
open source projects.
As the digital processing core of the USRP-LW 2950 the XC7K410T FPGA provides high-speed connectivity between all
major components. Includes RF front end, host interface, and DDR3
memory. The default FPGA provides all UHDs for controlling digital
downconversion and digital upconversion, fine frequency tuning, and
some other DSP function blocks. Users can take advantage of the
spare space of the resource-rich Kintex-7 FPGA, plus the RFNoC
development framework supported by USRP, to develop and implement
their own DSP processing modules.
The USRP-LW 2950 Equipment Kit includes: one USRP-LW 2950 main unit, Gigabit cable, SFP+ Gigabit adapter, power adapter,
USB2.0 JTAG cable, SMA connector RF cable 4 root.
TheUSRP-LW 2950 offers a variety of high-speed interfaces to choose from. On the
panel of the device, the Gigabit Ethernet port is one of the
simplest and most commonly used ways to connect. For applications
with extended bandwidth and low latency, such as PHY/MAC studies,
the X310 provides an efficient bus interface PCIe x4 for this
deterministic operation. When the application uses network
recording or multi-node processing, 10 Gigabit port is the best
choice.
The USRP-LW 2950 includes many additional features that will help some other
wireless applications. For example, in FPGA design, the 1GB DDR3 on
the motherboard can be used as data buffering and data storage. The
internal GPSDO provides high-precision frequency reference when
synchronized to the GPS system with a synchronization delay of less
than 50ns. Allows the user to control external components such as
amplifiers and switches through the GPIO interface, support inputs
such as event triggers, and observe debug signals. The USRP-LW 2950 also includes an internal JTAG adapter that allows developers to
easily load and debug new FPGA images.
