AM29F040B-70JD 8 pin ic chip Integrated Circuit Chip CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Am29F040B

4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

• 5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

• Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F040 device

• High performance

— Access times as fast as 55 ns

• Low power consumption

— 20 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby current (standard access time to active mode)

• Flexible sector architecture

— 8 uniform sectors of 64 Kbytes each

— Any combination of sectors can be erased

— Supports full chip erase

— Sector protection: A hardware method of locking sectors to prevent any program

or erase operations within that sector

• Embedded Algorithms

— Embedded Erase algorithm automatically preprograms and erases the entire chip

or any combination of designated sectors

— Embedded Program algorithm automatically writes and verifies bytes at specified addresses

• Minimum 1,000,000 program/erase cycles per sector guaranteed

• 20-year data retention at 125°C

— Reliable operation for the life of the system

• Package options

— 32-pin PLCC, TSOP, or PDIP

• Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply Flash standard

— Superior inadvertent write protection

• Data# Polling and toggle bits

— Provides a software method of detecting program or erase cycle completion

• Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data from, or program data to, a non-erasing sector,

then resumes the erase operation

GENERAL DESCRIPTION

The Am29F040B is a 4 Mbit, 5.0 volt-only Flash memory organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of data are divided into eight sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0–DQ7. The Am29F040B is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt V_CC supply. A 12.0 volt V_PP is not required for write or erase operations. The device can also be programmed in standard EPROM programmers.

This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and benefits of the Am29F040, which was manufactured using 0.5 µm process technology. In addtion, the Am29F040B has a second toggle bit, DQ2, and also offers the ability to program in the Erase Suspend mode.

The standard Am29F040B offers access times of 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.

The system can place the device into the standby mode. Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

A9, OE# (Note 2). . . . . . . . . . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 5. Maximum DC voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 6.

2. Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and OE# may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 5. Maximum DC input voltage on A9 and OE# is 12.5 V which may overshoot to 13.5 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 5. Maximum Negative Overshoot Waveform

Figure 6. Maximum Positive Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CC Supply Voltages

V_CC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V

V_CC for ± 10% devices . . . . . . . . . . . +4.5 V to +5.5 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

BLOCK DIAGRAM

CONNECTION DIAGRAMS

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