20 18 CS Chip Select. Active low logic input. This input provides
the dual function of initiating conversions on the AD7490 and also frames the serial data transfer. 23 21 REFIN Reference Input for the AD7490. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 22 20 VDD Power Supply Input. The VDD range for the AD7490 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, VDD should be from 4.75 V to 5.25 V. 14, 21, 24 12, 19, 22 AGND Analog Ground. Ground reference point
for all circuitry on the AD7490. All analog/digital input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 13 to 5, 11 to 9, VIN0 to VIN15 Analog Input 0 through Analog Input 15. Sixteen single-ended 3 to 1, 7 to 2, analog input channels that are multiplexed into the
on chip 28 to 25 31 to 26, track-and-hold. The analog input channel to be
converted is 24 selected by using the address bits ADD3 through ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequence register to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. 19 17 DIN Data In. Logic input. Data to be written to the control
register of the AD7490 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). 15 13 DOUT Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided by MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 16 14 SCLK Serial Clock. Logic input. SCLK provides the serial
clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7490. 17 15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7490 operates. N/A EP EPAD Exposed Pad. Connect exposed pad to GND. | 
