1 Mbit serial IC bus EEPROM Integrated Circuit Ic Chip M24M01-RMN6TP

Description

The M24M01-R is an I2C-compatible electrically erasable programmable memory (EEPROM) device organized as 128 Kb × 8 bits. The I2C bus is a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The M24M01-R behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are generated by the bus master and initiated by a Start condition, followed by the device select code, address bytes and data bytes. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. In order to meet environmental requirements, ST offers the M24M01-R in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 4.

Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C

bus at maximum frequency fC = 400 kHz

Device operation

The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24M01-R device is always a slave in all communication.

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