Standard Invensys Triconex 3008 Main Processor Architecture Tricon V9.6 And Later Systems

Product:TRICONEX Invensys 3008

Main Processor Architecture Tricon v9.6 and later systems

Model 3008 Main Processors (MP) are available for Tricon v9.6 and later systems. For detailed specifications, see the Planning and Installation Guide for Tricon Systems. Three MPs must be installed in the Main Chassis of every Tricon system. Each MP independently communicates with its I/O subsystem and executes the user-written control program.

During each scan, the MPs inspect designated discrete variables for state changes known as events. When an event occurs, the MPs save the current variable state and time stamp in the buffer of an SOE block.

If multiple Tricon systems are connected by means of NCMs, the time synchronization capability ensures a consistent time base for effective SOE time-stamping.

Microprocessor

Motorola MPC860, 32 bit, 50 MHz

Memory

• 16 MB DRAM (non-battery backed-up) • 32 KB SRAM, battery backed-up • 6 MB Flash PROM

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