Inputs: 16 single-ended or 8 differential voltage inputs Interfaces to current inputs via external 250 Ω resistors (included
in analog input termination blocks, catalog number T3325XX) | Fault-Tolerant Operation: Supports parallel connection with redundant modules of the same
type |
Hot Replaceable: Allows module replacement without system shutdown | Configurable Input Ranges: Jumper-selectable for flexibility |
High-Resolution Conversion: 12-bit analog-to-digital resolution (1 part in 4096) | Sample Rate: All channels: 1.8 ms (differential) or 3.6 ms (single-ended) |
Special Versions Available: 60 Hz rejection (T3420A) Fast response (T3420AF) | Electrical Isolation: 2500 V isolation between analog and digital logic circuits |
Front Panel Indicators: Individual LEDs show module active and fault status | Certification: TÜV certified for safety, Risk Class 5 |
1:Signal Conditioning & Conversion
Analog field signals are conditioned and multiplexed into an
analog-to-digital (A/D) converter.
Signals are converted into 12-bit digital data, which is stored in
the module’s RAM.
Digital logic circuits are optically isolated from analog signals
to protect against field transients and overvoltages.
2:Data Requests from Processor Modules
Processor modules send triplicated read data requests over the I/O
Safetybus.
The module votes the processors’ addressing and data requests,
preventing upstream I/O Safetybus failures from affecting module
operation.
The voted result is passed to the I/O bus interface logic.:
3:Retrieving Analog Data
Upon receiving the voted read request, the I/O bus interface logic
retrieves the analog data values from RAM.
Data is then placed into the module’s three bus drivers, each
independently powered and controlled by the I/O transceiver
modules.
This architecture prevents a failure in one driver from affecting
the other two I/O busses.
4:Data Transmission to Processors
The bus drivers transmit the data via the backplane I/O Safetybus
to the I/O transceiver modules, which forward the data to the
processors.
5:Data Packaging
The 12-bit analog input data is packaged as a 16-bit integer:
The least significant 12 bits represent the analog value (0–4095).
Two of the remaining four bits are used to flag alarms (as shown in
Figure 2).
1:Voter Circuit Testing
Each module’s voter circuits are periodically tested by the
processor modules.
Discrepant data are sent through one of the three legs of the I/O
Safetybus to check whether the module can outvote incorrect data.
Failure to return the correct majority-voted result triggers:
An I/O module error indication at the processor modules
A module fault indication at the I/O module
2:Module Identification
Each module type has a unique identification code read by the
controller.
This code allows the controller to:
Determine the type of module installed in each I/O chassis slot
Address the module and its points correctly
If a module is removed or replaced with a different type, the
processor modules generate an I/O module error.
3:Loopback Logic Testing
Periodically, data is written to the module and then read back.
This verifies that the module’s I/O bus interface logic is
functioning correctly.
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