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100Gbps QSFP28 LR4 Transceiver with DDM 10KM Wavelength Range 1310nm-1550nm

    Buy cheap 100Gbps QSFP28 LR4 Transceiver with DDM 10KM Wavelength Range 1310nm-1550nm from wholesalers
     
    Buy cheap 100Gbps QSFP28 LR4 Transceiver with DDM 10KM Wavelength Range 1310nm-1550nm from wholesalers
    • Buy cheap 100Gbps QSFP28 LR4 Transceiver with DDM 10KM Wavelength Range 1310nm-1550nm from wholesalers

    100Gbps QSFP28 LR4 Transceiver with DDM 10KM Wavelength Range 1310nm-1550nm

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    Brand Name : TAKFLY
    Model Number : TK-B3524-3LCD2
    Certification : CE,ROHS,REACH,ISO9001,ISO14001
    Price : US$0.01 ~ US$1200/PC
    Payment Terms : L/C, D/A, D/P, T/T, Western Union, MoneyGram
    Delivery Time : 3-7working days
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    100Gbps QSFP28 LR4 Transceiver with DDM 10KM Wavelength Range 1310nm-1550nm

    Description
    • This product is a 100Gb/s transceiver module designed for optical communication applications compliant to 100GBASE-LR4 of the IEEE P802.3ba standard. The module converts 4 input channels of 25Gb/s electrical data to 4 channels of LAN WDM optical signals and then multiplexes them into a single channel for 100Gb/s optical transmission. Reversely on the receiver side, the module de-multiplexes a 100Gb/s optical input into 4 channels of LAN WDM optical signals and then converts them to 4 output channels of electrical data.
    • The central wavelengths of the 4 LAN WDM channels are 1295.56, 1300.05, 1304.58 and 1309.14 nm as members of the LAN WDM wavelength grid defined in IEEE 802.3ba. The high performance cooled LAN WDM EA-DFB transmitters and high sensitivity PIN receivers provide superior performance for 100Gigabit Ethernet applications up to 10km links and compliant to optical interface with IEEE802.3ba Clause 88 100GBASE-LR4 requirements.
    • The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

    Features

    • Hot pluggable QSFP28 MSA form factor
    • Compliant to IEEE 802.3ba 100GBASE-LR4
    • Up to 10km reach for G.652 SMF
    • Single +3.3V power supply
    • Operating case temperature: 0~70℃
    • Transmitter: cooled 4x25Gb/s LAN WDM EML TOSA (1295.56, 1300.05, 1304.58, 1309.14nm)
    • Receiver: 4x25Gb/s PIN ROSA
    • 4x28G Electrical Serial Interface (CEI-28G-VSR)
    • Maximum power consumption 4.0W
    • Duplex LC receptacle

    Applications

    • 100GBASE-LR4 Ethernet Links
    • Infiniband QDR and DDR interconnects
    • Client-side 100G Telecom connections

    Functional Description

    1. The transceiver module receives 4 channels of 25Gb/s electrical data, which are processed by a 4-channel Clock and Data Recovery (CDR) IC that reshapes and reduces the jitter of each electrical signal. Subsequently, each of 4 EML laser driver IC's converts one of the 4 channels of electrical signals to an optical signal that is transmitted from one of the 4 cooled EML lasers which are packaged in the Transmitter Optical Sub-Assembly (TOSA). Each laser launches the optical signal in specific wavelength specified in IEEE802.3ba 100GBASE-LR4 requirements. These 4-lane optical signals will be optically multiplexed into a single fiber by a 4-to-1 optical WDM MUX. The optical output power of each channel is maintained constant by an automatic power control (APC) circuit. The transmitter output can be turned off by TX_DIS hardware signal and/or 2-wire serial interface.
    2. The receiver receives 4-lane LAN WDM optical signals. The optical signals are de-multiplexed by a 1-to-4 optical DEMUX and each of the resulting 4 channels of optical signals is fed into one of the 4 receivers that are packaged into the Receiver Optical Sub-Assembly (ROSA). Each receiver converts the optical signal to an electrical signal. The regenerated electrical signals are retimed and de-jittered and amplified by the RX portion of the 4-channel CDR. The retimed 4-lane output electrical signals are compliant with IEEE CAUI-4 interface requirements. In addition, each received optical signal is monitored by the DOM section. The monitored value is reported through the 2-wire serial interface. If one or more received optical signal is weaker than the threshold level, RX_LOS hardware alarm will be triggered.

    3. A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and VccRx are internally connected and should be applied concurrently. As per MSA specifications the module offers 7 low speed hardware control pins (including the 2-wire serial interface): ModSelL, SCL, SDA, ResetL, LPMode, ModPrsL and IntL.

    4. Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire serial communication commands. The ModSelL allows the use of this product on a single 2-wire interface bus – individual ModSelL lines must be used.

    5. Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the QSFP28 memory map.

    6. The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

    7. Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order to protect hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted.

      Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.

    8. Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

    Transceiver Block Diagram

    Figure 1. Transceiver Block Diagram


    Pin Assignment and Description

    Figure 2. MSA compliant Connecto


    Pin Definition


    PINLogicSymbolName/DescriptionNote s
    1GNDGround1
    2CML-ITx2nTransmitter Inverted Data Input
    3CML-ITx2pTransmitter Non-Inverted Data output
    4GNDGround1
    5CML-ITx4nTransmitter Inverted Data Input
    6CML-ITx4pTransmitter Non-Inverted Data output
    7GNDGround1
    8LVTLL-IModSelLModule Select
    9LVTLL-IResetLModule Reset
    10VccRx+3.3V Power Supply Receiver2
    11LVCMOS-I/OSCL2-Wire Serial Interface Clock
    12LVCMOS-I/OSDA2-Wire Serial Interface Data
    13GNDGround
    14CML-ORx3pReceiver Non-Inverted Data Output
    15CML-ORx3nReceiver Inverted Data Output
    16GNDGround1
    17CML-ORx1pReceiver Non-Inverted Data Output
    18CML-ORx1nReceiver Inverted Data Output
    19GNDGround1
    20GNDGround1
    21CML-ORx2nReceiver Inverted Data Output
    22CML-ORx2pReceiver Non-Inverted Data Output
    23GNDGround1
    24CML-ORx4nReceiver Inverted Data Output1
    25CML-ORx4pReceiver Non-Inverted Data Output
    26GNDGround1
    27LVTTL-OModPrsLModule Present
    28LVTTL-OIntLInterrupt
    29VccTx+3.3 V Power Supply transmitter2
    30Vcc1+3.3 V Power Supply2
    31LVTTL-ILPModeLow Power Mode
    32GNDGround1
    33CML-ITx3pTransmitter Non-Inverted Data Input
    34CML-ITx3nTransmitter Inverted Data Output
    35GNDGround1
    36CML-ITx1pTransmitter Non-Inverted Data Input
    37CML-ITx1nTransmitter Inverted Data Output
    38GNDGround1

    Notes:

    1. GND is the symbol for signal and supply (power) common for the QSFP28 module. All are common within the module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
    2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown in Figure 3 below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the module in any combination. The connector pins are each rated for a maximum current of 1000mA.

    Recommended Power Supply Filter

    Figure 3. Recommended Power Supply Filter

    Absolute Maximum Ratings

    It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.

    ParameterSymbolMinMaxUnitsNotes
    Storage TemperatureTS-4085degC
    Operating Case TemperatureTOP070degC
    Power Supply VoltageVCC-0.53.6V
    Relative Humidity (non-condensation)RH085%
    Damage Threshold, each LaneTHd5.5dBm

    Recommended Operating Conditions and Power Supply Requirements

    ParameterSymbolMinTypicalMaxUnits
    Operating Case TemperatureTOP070degC
    Power Supply VoltageVCC3.1353.33.465V
    Data Rate, each Lane25.78125Gb/s
    Control Input Voltage High2VccV
    Control Input Voltage Low00.8V
    Link Distance with G.652D0.00210km

    Electrical Characteristics

    The following electrical characteristics are defined over the Recommended Operating Environment unless otherwise specified.

    ParameterSymbolMinTypicalMaxUnitsNotes
    Power Consumption4.0W
    Supply CurrentIcc1.21A
    Transceiver Power-on Initialization Time

    2000


    ms


    1

    Transmitter (each Lane)

    Single-ended Input Voltage Tolerance (Note 2)


    -0.3


    4.0


    V

    Referred to TP1 signal common

    AC Common Mode Input

    Voltage Tolerance


    15


    mV


    RMS

    Differential Input Voltage Swing Threshold

    50


    mVpp

    LOSA

    Threshold

    Differential SwingInputVoltage

    Vin,pp


    190


    700


    mVpp

    Differential Input ImpedanceZin90100110Ohm
    Receiver (each Lane)

    Single-ended Voltage


    Output


    -0.3


    4.0


    V

    Referred to signal

    common

    AC Common Mode Output

    Voltage


    7.5


    mV


    RMS

    Differential Output Voltage Swing

    Vout,pp


    300


    850


    mVpp

    Differential ImpedanceOutput

    Zout


    90


    100


    110


    Ohm

    Notes:

    1.Power-on Initialization Time is the time from when the power supply voltages reach and remain above the

    minimum recommended operating supply voltages to the time when the module is fully functional.

    2.The single ended input voltage tolerance is the allowable range of the instantaneous input signals


    Optical Characteristics


    QSFP28 100GBASE-LR4
    ParameterSymbolMinTypicalMaxUnitNotes

    Lane Wavelength

    L01294.531295.561296.59nm
    L11299.021300.051301.09nm
    L21303.541304.581305.63nm
    L31308.091309.141310.19nm
    Transmitter
    Side Mode Suppression RatioSMSR30dB
    Total Average Launch PowerPT10.5dBm
    Average Launch Power, each Lane

    PAVG


    -4.3


    4.5


    dBm

    OMA, each LanePOMA-1.34.5dBm1
    Difference in Launch Power between any Two Lanes (OMA)

    Ptx,diff


    5


    dB

    Launch Power in OMA minus Transmitter and Dispersion

    -2.3


    dBm

    Penalty (TDP), each Lane
    TDP, each LaneTDP2.2dB
    Extinction RatioER4dB
    RIN20OMARIN-130dB/Hz
    Optical Return Loss ToleranceTOL20dB
    Transmitter ReflectanceRT-12dB
    Eye Mask{X1, X2, X3, Y1, Y2, Y3}

    {0.25, 0.4, 0.45, 0.25, 0.28, 0.4}


    2

    Average Launch Power OFF

    Transmitter, each Lane


    Poff


    -30


    dBm

    Receiver
    Damage Threshold, each LaneTHd5.5dBm3
    Total Average Receive Power10.5dBm
    Average Receive Power, each Lane

    -10.6


    4.5


    dBm

    Receive Power (OMA), each

    Lane


    4.5


    dBm

    Receiver Sensitivity (OMA), each Lane

    SEN


    -8.6


    dBm

    Stressed Receiver Sensitivity

    (OMA), each Lane


    -6.8


    dBm


    4

    Receiver ReflectanceRR-26dB

    Difference in Receive Power

    between any Two Lanes (OMA)


    Prx,diff


    5.5


    dB

    LOS AssertLOSA-18dBm
    LOS DeassertLOSD-15dBm
    LOS HysteresisLOSH0.5dB
    Receiver Electrical 3 dB upper Cutoff Frequency, each Lane

    Fc


    31


    GHz

    Conditions of Stress Receiver Sensitivity Test (Note 5)
    Vertical Eye Closure Penalty, each Lane

    1.8


    dB

    Stressed Eye J2 Jitter, each Lane0.3UI
    Stressed Eye J9 Jitter, each Lane0.47UI

    Notes:

    1.Even if the TDP < 1 dB, the OMA min must exceed the minimum value specified here.

    2.See Figure 4 below.

    3.The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal

    having this power level on one lane. The receiver does not have to operate correctly at this input power.

    4.Measured with conformance test signal at receiver input for BER = 1x10-12.

    5.Vertical eye closure penalty and stressed eye jitter are test conditions for measuring stressed receiver sensitivity. They are not characteristics of the receiver.


    Digital Diagnostic Functions

    The following digital diagnostic characteristics are defined over the normal operating conditions unless otherwise specified.

    ParameterSymbolMinMaxUnitsNotes
    Temperature monitor absolute error

    DMI_Temp


    -3


    +3


    degC

    Over operating temperature range

    Supply voltage monitor

    absolute error


    DMI _VCC


    -0.1


    0.1


    V

    Over full operating

    range

    Channel RX power monitor absolute error

    DMI_RX_Ch


    -2


    2


    dB


    1

    Channel Bias current

    monitor

    DMI_Ibias_Ch-10%10%mA

    Channel TX power

    monitor absolute error

    DMI_TX_Ch-22dB1

    Notes:

    Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB fluctuation, or a +/- 3 dB total accuracy.


    Mechanical Dimensions

    Figure 5. Mechanical Outline


    ESD

    This transceiver is specified as ESD threshold 1KV for high speed data pins and 2KV for all others electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However, normal ESD precautions are still required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and handled only in an ESD protected environment.


    Laser Safety

    This is a Class 1 Laser Product according to EN 60825-1:2014. This product complies with 21 CFR 1040.10 and 1040.11 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).

    Caution: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.


    Regulatory Compliance

    FeatureReferencePerformance

    Electrostatic discharge(ESD)


    IEC/EN 61000-4-2


    Compatible with standards


    Electromagnetic Interference (EMI)

    FCC Part 15 Class B EN 55022 Class B

    (CISPR 22A)


    Compatible with standards


    Laser Eye Safety

    FDA 21CFR 1040.10, 1040.11 IEC/EN

    60825-1, 2


    Class 1 laser product

    Component RecognitionIEC/EN 60950, ULCompatible with standards
    ROHS2002/95/ECCompatible with standards
    EMCEN61000-3Compatible with standards
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