SRAM 18Mbit Static RAM High-performance COMS Static Random Access
Memory CY7C1381KV33-133AXI
Features■ Supports 133 MHz bus operations■ 512K × 36 and 1M × 18
common I/O■ 3.3 V core power supply (VDD)■ 2.5 V or 3.3 V I/O
supply (VDDQ)■ Fast clock-to-output time❐ 6.5 ns (133 MHz version)■
Provides high performance 2-1-1-1 access rate■ User selectable
burst counter supporting interleaved or linearburst sequences■
Separate processor and controller address strobes■ Synchronous
self-timed write■ Asynchronous output enable■
CY7C1381KV33/CY7C1381KVE33 available inJEDEC-standard Pb-free
100-pin TQFP, Pb-free 165-ballFBGA package.
CY7C1383KV33/CY7C1383KVE33 availablein JEDEC-standard Pb-free
100-pin TQFP.■ IEEE 1149.1 JTAG-Compatible Boundary Scan■ ZZ sleep
mode option.■ On-chip error correction code (ECC) to reduce soft
error rate(SER)
Functional DescriptionThe
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33 are a 3.3 V,
512K × 36 and 1M × 18synchronous flow through SRAMs, designed to
interface withhigh speed microprocessors with minimum glue logic.
Maximumaccess delay from clock rise is 6.5 ns (133 MHz version). A
2-biton-chip counter captures the first address in a burst
andincrements the address automatically for the rest of the
burstaccess. All synchronous inputs are gated by registers
controlledby a positive edge triggered clock input (CLK). The
synchronousinputs include all addresses, all data inputs, address
pipeliningchip enable (CE1), depth-expansion chip enables (CE2
andCE3), burst control inputs (ADSC, ADSP, and ADV), writeenables
(BWx, and BWE), and global write (GW). Asynchronousinputs include
the output enable (OE) and the ZZ pin.The
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33 allows
interleaved or linear burst sequences,selected by the MODE input
pin. A HIGH selects an interleavedburst sequence, while a LOW
selects a linear burst sequence.Burst accesses can be initiated
with the processor addressstrobe (ADSP) or the cache controller
address strobe (ADSC)inputs. Address advancement is controlled by
the addressadvancement (ADV) input.Addresses and chip enables are
registered at rising edge ofclock when address strobe processor
(ADSP) or address strobecontroller (ADSC) are active. Subsequent
burst addresses canbe internally generated as controlled by the
advance pin
(ADV).CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33
operates from a +3.3 V core power supplywhile all outputs operate
with a +2.5 V or +3.3 V supply. All inputsand outputs are
JEDEC-standard and JESD8-5-compatible.
Packaging and transportation instructions
- According to the standard export packaging.
Customers can choose from cartons, wooden cases and wooden pallets
according to their own requirements.
Q&A
1. How to obtain the price?
We usually quote within 24 hours after receiving your inquiry
(except weekends and holidays). If you are in urgent need of a
price, please send us an email or contact us in any other way so
that we can provide you with a quotation.
2. What is your delivery time?
This depends on the quantity of the order and the season in which
you place the order. Usually, we can ship the goods within 7 to 15
days (for small batches), and for large batches, it takes about 30
days.
3. What are your payment terms?
Factory price, 30% deposit, 70%T/T payment before shipment.
4. What is the mode of transportation?
It can be transported by sea, air or express delivery (EMS, UPS,
DHL, TNT, FEDEX, etc.). Please confirm with us before placing an
order.
5. How do you help our business establish a long-term and good
relationship?
We maintain good quality and competitive prices to ensure that our
customers benefit.
2. We respect every customer as our friend. We do business with
them sincerely and make friends with them, no matter where they
come from.
