100Gbps QSFP28 ER4 Lite Optical Transceiver Up to 27.952 Gbps Data rate per channel

100Gbps QSFP28 ER4 Lite Optical Transceiver Up to 27.952 Gbps Data rate per channel

• TKQS28-100G-ER4 is a 100Gb/s transceiver module designed for optical communication applications compliant to Ethernet 100GBASE-ER4 Lite standard. The module converts 4 input channels of 25Gb/s electrical data to 4 channels of LANWDM optical signals and then multiplexes them into a single channel for 100Gb/s optical transmission. Reversely on the receiver side, the module de-multiplexes a 100Gb/s optical input into 4 channels of LANWDM optical signals and then converts them to 4 output channels of electrical data.
• The central wavelengths of the 4 LAN WDM channels are 1295.56, 1300.05, 1304.58 and 1309.14nm as members of the LANWDM wavelength grid defined in IEEE802.3ba.The high performance cooled LAN WDM EA-DFB transmitters and high sensitivity APD receivers provide superior performance for 100Gigabit Ethernet applications up to 30km links without FEC and 40km links with FEC.
• The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA).It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

Functional Description

1. The transceiver module receives 4 channels of 25Gb/s electrical data, which are processed by a 4-channel Clock and Data Recovery (CDR) IC that reshapes and reduces the jitter of each electrical signal. Subsequently, EML laser driver IC converts each one of the 4 channels of electrical signals to an optical signal that is transmitted from one of the 4 cooled EML lasers which are packaged in the Transmitter Optical Sub-Assembly (TOSA). Each laser launches the optical signal in specific wavelength specified in IEEE802.3ba 100G BASE-ER4 requirements. These 4-lane optical signals will be optically multiplexed into a single fiber by a 4-to-1 optical WDMMUX. The optical output power of each channel is maintained constant by an automatic power control (APC) circuit. The transmitter output can be turned off by TX_DIS hardware signal and/or 2-wire serial interface.

• The receiver receives 4-lane LANWDM optical signals. The optical signals are de-multiplexed by a 1-to-4 optical DEMUX and each of the resulting 4 channels of optical signals is fed into one of the 4 receivers that are packaged into the Receiver Optical Sub-Assembly (ROSA). Each receiver converts the optical signal to an electrical signal. The regenerated electrical signals are retimed and de-jittered and amplified by the RX portion of the 4-channel CDR. The retimed 4-lane output electrical signals are compliant with CEI-28G-VSR interface requirements. In addition, each received optical signal is monitored by the DOM section. The monitored value is reported through the 2-wire serial interface. If one or more received optical signal is weaker than the threshold level, RX_LOS hardware alarm will be triggered.
• A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and VccRx are internally connected and should be applied concurrently. As per MSA specifications the module offers 7 low speed hardware control pins (includingthe2-wireserialinterface): ModSelL, SCL, SDA, ResetL, LPMode, ModPrsL and IntL.
• Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire serial communication commands. The ModSelL allows the use of this product on a single2-wireinterface bus – individual ModSelL lines must be used.
• Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the QSFP28 memory map.
• The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.
• Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order to protect hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted
• Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.
• Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

Features

Ø Hot pluggable QSFP28 MSA form factor

Ø Compliant to Ethernet 100GBASE-ER4 Lite

Ø Supports 103.1Gb/s aggregate bit rate

Ø Up to 30km reach for G.652 SMF without FEC

Ø Up to 40km reach for G.652 SMF with FEC

Ø Single +3.3V power supply

Ø Operating case temperature: 0~70oC

Ø Transmitter: cooled 4x25Gb/s LAN WDM EML TOSA (1295.56, 1300.05, 1304.58, 1309.14nm)

Ø Receiver: 4x25Gb/s APD ROSA

Ø 4x25G electrical interface (OIF CEI-28G-VSR)

Ø Maximum power consumption 4.5W

Ø Duplex LC receptacle

Ø RoHS-6 compliant

Applications

Ø 100GBASE-LR4 Ethernet Links

Ø Infiniband QDR and DDR interconnects

Ø Client-side 100G Telecom connections

Transceiver Block Diagram

Figure 1. Transceiver Block Diagram

Pin Assignment and Description

Figure 2. MSA compliant Connector

TAKFLY COMMUNICATIONS CO., LTD.