PEX8716-BA80BC G 4.3W 19mm Length Integrated Circuit Chips

■ Hi Performance
♦ performancePAK
- Read Pacing (bandwidth throttling)
- Multicast
- Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 112ns max packet latency (x4 to x4)
- 2KB Max Payload Size

■ Flexible Configuration
- Ports configurable as x1, x2, x4, x8
- Registers configurable with strapping 2 pins, EEPROM, I C, or host software
- Lane and polarity reversal
- Compatible with PCIe 1.0a PM

■ Multi-Host & Fail-Over Support
- Configurable Non-Transparent (NT) port
- Failover with NT port
- Up to 2 upstream/Host ports with 1+1 or N+1 failover to other upstream ports

■ Quality of Service (QoS)
- Eight traffic classes per port
- Weighted round-robin source port arbitration

The PEX 8716’s 4 ports can be configured to lane widths of x1, x2, x4, or x8. Flexible buffer allocation, along with the device's flexible packet
flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port
can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8716’s common port
configurations in legacy Single-Host mode.