XC5VLX110-2FFG676I 440 I/O 550MHz Xilinx Virtex 5

• Advanced DSP48E slices
− 25 x 18, two’s complement, multiplication
− Optional adder, subtracter, and accumulator
− Optional pipelining
− Optional bitwise logical functionality
− Dedicated cascade connections

• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback reconfiguration logic
− Auto bus width detection capability

• System Monitoring capability on all devices
− On-chip/Off-chip thermal monitoring
− On-chip/Off-chip power supply monitoring
− JTAG access to all monitored quantities

• Integrated Endpoint blocks for PCI Express Designs
− LXT, SXT, TXT, and FXT Platforms
− Compliant with the PCI Express Base Specification 1.1
− x1, x4, or x8 lane support per block
− Works in conjunction with RocketIO™ transceivers

• Most advanced, high-performance, optimal-utilization, FPGA fabric
− Real 6-input look-up table (LUT) technology
− Dual 5-LUT option
− Improved reduced-hop routing
− 64-bit distributed RAM option
− SRL32/Dual SRL16 option