XC2VP40-6FF1152I 350MHz 692 I/O Virtex II Pro

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Brand Name :	Xilinx Inc.
Model Number :	XC2VP40-6FF1152I
Certification :	Lead free / RoHS Compliant
Price :	USD 10000~15000 pcs
Payment Terms :	T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :	68 pcs
Delivery Time :	3-5 Day

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XC2VP40-6FF1152I 350MHz 692 I/O Virtex II Pro

XC2VP40-6FF1152I IC FPGA FBGA-1152 692 I/O Virtex-II Pro

Product Attribute	Attribute Value
Manufacturer:	Xilinx
Product Category:	FPGA - Field Programmable Gate Array
Product:	Virtex-II Pro
Number of Logic Elements:	43632
Number of I/Os:	692 I/O
Operating Supply Voltage:	1.5 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 100 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-1152
Data Rate:	6.25 Gb/s
Series:	XC2VP40
Brand:	Xilinx
Distributed RAM:	606 kbit
Embedded Block RAM - EBR:	3456 kbit
Maximum Operating Frequency:	350 MHz
Moisture Sensitive:	Yes
Number of Transceivers:	12 Transceiver
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	1
Subcategory:	Programmable Logic ICs
Tradename:	Virtex

Virtex-II Pro Platform FPGA Technology

• SelectRAM+ Memory Hierarchy
- Up to 8 Mb of True Dual-Port RAM in 18 Kb block SelectRAM+ resources
- Up to 1,378 Kb of distributed SelectRAM+ resources
- High-performance interfaces to external memory

• Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains

• Flexible Logic Resources
- Up to 88,192 internal registers/latches with Clock Enable
- Up to 88,192 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products support
- Internal 3-state busing

• High-Performance Clock Management Circuitry
- Up to twelve Digital Clock Manager (DCM) modules
· Precise clock de-skew
· HyperTransport (LDT) I/O with current driver buffers
· Built-in DDR input and output registers

Array Overview

Virtex-II Pro and Virtex-II Pro X devices are user-programmable gate arrays with various configurable elements and
embedded blocks optimized for high-density and high-performance system designs.

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