EP2S90F780C4N 620mA 534 I/O ALTERA FPGA Chip

■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
■ TriMatrixmemory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting