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EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA

    Buy cheap EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA from wholesalers
     
    Buy cheap EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA from wholesalers
    • Buy cheap EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA from wholesalers

    EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA

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    Brand Name : Intel / Altera
    Model Number : EP4SGX360NF45I4N
    Certification : Lead free / RoHS Compliant
    Price : USD 12000-15000 pcs
    Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card
    Supply Ability : 80 pcs
    Delivery Time : 3-5 Day
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    EP4SGX360NF45I4N 920 I/O 600MHz Stratix IV FPGA

    EP4SGX360NF45I4N ALTERA FPGA Chip FBGA-1932 920 I/O Stratix IV GX


    Product AttributeAttribute Value
    Intel
    FPGA - Field Programmable Gate Array
    Stratix IV GX
    353600
    14144
    920 I/O
    900 mV
    - 40 C
    + 85 C
    SMD/SMT
    FBGA-1932
    Tray
    Data Rate:600 Mb/s to 8.5 Gb/s
    Series:Stratix IV GX
    Brand:Intel / Altera
    Maximum Operating Frequency:600 MHz
    Moisture Sensitive:Yes
    Number of Transceivers:48 Transceiver
    Product Type:FPGA - Field Programmable Gate Array
    Factory Pack Quantity:12
    Subcategory:Programmable Logic ICs
    Total Memory:22564 kbit
    Tradename:Stratix
    Part # Aliases:974496


    Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device:
    ■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support
    data rates between 600 Mbps and 8.5 Gbps
    ■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbp
    ■ Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,
    SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken
    ■ Root complex and end-point applications
    ■ x1, x4, and x8 lane configurations
    ■ PIPE 2.0-compliant interface
    ■ Embedded circuitry to switch between Gen1 and Gen2 data rates
    ■ Built-in circuitry for electrical idle generation and detection, receiver detect, power state transitions, lane reversal, and polarity inversion
    ■ 8B/10B encoder and decoder, receiver synchronization state machine, and ± 300 parts per million (ppm) clock compensation circuitry
    ■ Transaction layer support for up to two virtual channels (VCs)
    ■ XAUI/HiGig Support
    ■ Compliant to IEEE802.3ae specification
    ■ Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from idle ordered sets (||A||, ||K||, ||R||) at the transmitter and
    receiver, respectively
    ■ 8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and ± 100 ppm clock compensation circuitry



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