5SGSMD5K2F40I3N 172600 LABs 696 I/O Stratix V GS

• Enhanced ALM with four registers
• Improved routing architecture reduces congestion and improves compile times
• M20K: 20-Kbit with hard error correction code (ECC)
• MLAB: 640-bit
• Up to 600 MHz performance
• Natively support signal processing with precision ranging from 9x9 up to 54x54
• New native 27x27 multiply mode
• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
• Embedded internal coefficient memory
• Pre-adder/subtractor improves efficiency
• Increased number of outputs allows more independent multipliers
• Fractional mode with third-order delta-sigma modulation
• Integer mode
• Precision clock synthesis, clock delay compensation, and zero delay buffer (ZDB)
• 800-MHz fabric clocking
• Global, quadrant, and peripheral clock networks
• Unused clock networks can be powered down to reduce dynamic power
• Gigabit Ethernet (GbE) and XAUI PCS
• 10G Ethernet PCS
• Serial RapidIO® (SRIO) PCS
• Common Public Radio Interface (CPRI) PCS
• Gigabit Passive Optical Networking (GPON) PCS
• Programmable Power Technology
• Quartus II integrated PowerPlay Power Analysis