EP2S60F1020I4N 500mA 718 I/O Stratix II

Stratix® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures (M512 RAM,
M4K RAM, and M-RAM blocks), and digital signal processing (DSP) blocks.

Each LAB consists of eight adaptive logic modules (ALMs). An ALM is the Stratix II device family’s basic building block of logic providing
efficient implementation of user logic functions. LABs are grouped into rows and columns across the device.

M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are grouped into columns across the device in between certain LABs.