488 I/O ALTERA FPGA Chip

■ 48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table 1–1)
■ Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards
■ Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks
■ High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
■ Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
■ The only high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to protect designs
■ Robust on-chip hot socketing and power sequencing support
■ Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support
■ Built-in error correction coding (ECC) circuitry to detect and correct data errors in M144K TriMatrix memory blocks
■ Nios® II embedded processor support
■ Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)
■ Memory interface support with dedicated DQS logic on all I/O banks
■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks